System, method and article of manufacture for synchronization-free transmittal of neuron values in a hardware artificial neural networks

ABSTRACT

Computations in Artificial neural networks (ANNs) are accomplished using simple processing units, called neurons, with data embodied by the connections between neurons, called synapses, and by the strength of these connections, the synaptic weights. Crossbar arrays may be used to represent one layer of the ANN with Non-Volatile Memory (NVM) elements at each crosspoint, where the conductance of the NVM elements may be used to encode the synaptic weights, and a highly parallel current summation on the array achieves a weighted sum operation that is representative of the values of the output neurons. A method is outlined to transfer such neuron values from the outputs of one array to the inputs of a second array with no need for global clock synchronization, irrespective of the distances between the arrays, and to use such values at the next array, and/or to convert such values into digital bits at the next array.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No.15/410,769, filed Jan. 20, 2017 which is hereby incorporated byreference in its entirety.

BACKGROUND OF THE INVENTION Field of Invention

The present invention relates generally to the field of artificialneural networks (ANNs). More specifically, the present invention isrelated to a system, method and article of manufacture forsynchronization-free transmittal of neuron values in a hardwareartificial neural network.

Discussion of Related Art

Artificial neural networks (ANNs) are distributed computing systems,which consist of several neurons interconnected through connectionpoints called synapses. Each synapse encodes the strength of theconnection between the output of one neuron and the input of another.The output of each neuron is determined by the aggregate input receivedfrom other neurons that are connected to it, and thus by the outputs ofthese “upstream” connected neurons and the strength of the connectionsas determined by the synaptic weights. The ANN is trained to solve aspecific problem (e.g., pattern recognition) by adjusting the weights ofthe synapses such that a particular class of inputs produces a desiredoutput. The weight adjustment procedure is known as “learning.” Thereare many algorithms in the ANN literature for performing learning thatare suitable for various tasks such as image recognition, speechrecognition, language processing, etc. Ideally, these algorithms lead toa pattern of synaptic weights that, during the learning process,converges toward an optimal solution of the given problem.

An attractive implementation of ANNs uses some (e.g., CMOS) circuitry torepresent the neuron, the function of which is to integrate or sum theaggregate input from upstream neurons to which a particular neuron isconnected, and apply some nonlinear function of the input to derive theoutput of that neuron. Because in general, each neuron is connected tosome large fraction of the other neurons, the number of synapses(connections) is much larger than the number of neurons; thus, it isadvantageous to use some implementation of synapses that can achievevery high density on a neuromorphic computing chip. One attractivechoice is a non-volatile memory (NVM) technology such as resistiverandom access memory (RRAM) or phase-change memory (PCM). Anotherattractive choice is a capacitor-transistor pair. It should be notedthat while the following document will discuss NVM-based synapses, thetechniques, methods, and embodiments are equally relevant to systemsbased on capacitance-based synaptic elements. Since both positive andnegative (i.e., excitatory and inhibitory) weights are desired, onescheme uses a pair of NVM (or two capacitor-transistor pairs) torepresent the weight as the difference in conductance between the two(see M. Suri et al., IEDM Tech. Digest, 4.4 (2011)). This scheme isshown in FIG. 1 . FIG. 1 illustrates a layer of an ANN implemented on acrossbar array, with pairs of NVM conductances acting as synapticweights. The outputs of the upstream N_(i) neurons are summed inparallel through pairs of NVM conductances into the positive andnegative inputs of the downstream M_(i) neurons. This parallelism ishighly advantageous for efficient computation. It should be noted thatwhile a non-linear 2-terminal access device is shown in this scheme,3-terminal transistor access devices are equally relevant to thisdiscussion.

The accumulated currents can be mirrored and integrated onto an outputcapacitor, such that the final analog voltage is representative of theoutput value of one of the neurons. While this capacitor is ‘local’ tothis particular array and is an analog representation of its output,this value of the output neuron activation must be made available,preferably in a digital format, at the input of another ‘downstream’neural network layer implemented on a second crossbar array. This secondarray could be at an arbitrary distance away from the source/upstreamfirst crossbar array, and preferably, the CMOS chip would be designed insuch a way that the mapping between sets of array outputs and subsequentsets of next-array inputs may be chosen by the user at runtime ratherthan during fabrication.

FIG. 2 illustrates current mirrors that are used to replicate theinstantaneous currents in the crossbar onto an output stage, such thatthese currents are integrated onto an output capacitance whose finalvoltage represents the analog activation of the neuron Mi.

A simplified approximate method to convert an analog voltage to adigital value involves discharging the stored charge at a constantcurrent, and counting the number of clock pulses until the capacitor isfully discharged. While local digitization followed by transmittal tothe downstream array would be possible and potentially accurate, thiswould require very careful synchronization of clock signals all acrossthe system (with minimal clock skew), which could prove to be expensiveand power-hungry, if not impossible. The process of passing N suchdigital values (where N may be 100-1000) would then require qNindividual bus lines for parallel transmission, OR would requireserialization for slower transmission across fewer bus lines. Such anapproach would also require careful re-buffering of the digitized datasignals to avoid issues related to interconnect-induced slew (i.e., thephenomenon by which rising and falling edges of input signals becomeless ‘sharp’ due to resistive and capacitive effects as they propagatealong a metal wire) which carries an additional area penalty.

Thus, there is a need in the art for a technique, given one or moreanalog values encoded as voltages on a plurality of capacitances, toconvey these values to a bank of digital buffers located across anarbitrary distance across the chip.

Embodiments of the present invention are an improvement over prior artsystems and methods.

SUMMARY OF THE INVENTION

In one embodiment, the present invention provides a method fortransmitting signals from one region on-chip to another region on-chip,without using a global clock or other means of global synchronization,wherein the method comprises transmitting a plurality of analog signalson a plurality of transmission channels, all of the transmissionchannels sharing a common initialization trigger, by encoding each ofthe signals in the delay between the common initialization trigger and asubsequent unique termination trigger, so that each of the signals isaccurately digitized remotely, or to be used for direct integrationremotely, using a limited number of transmission channels.

In another embodiment, the present invention provides a methodimplemented in an Artificial Neural Network (ANN), the ANN comprising aplurality of neurons arranged in layers, the layers comprising at leastone upstream neuron layer and at least one downstream neuron layer, theoutput of the at least one upstream neuron layer connected to the inputof the at least one downstream neuron layer, the method comprising: (a)commencing discharging of a capacitor in the upstream neuron layer basedon an enable signal generated in the upstream neuron layer, thecapacitor having an initial value representative of an output of theupstream neuron layer; (b) sharing the enable signal in (a) to an inputof a digital counter located at the downstream neuron layer, where thecounter, upon reception of the enable signal, starts counting using aclock that is local to the downstream neuron layer; (c) monitoringoutput analog voltage of the capacitor; and (d) when a voltagetransition is detected in the monitored output analog voltage, (e)transmitting a voltage transition signal to the downstream neuron layer,wherein the downstream neuron layer latches a current value of thecounter upon reception of the voltage transition signal, the latchedcurrent value being equal to the initial value representative of anoutput of the upstream neuron layer, and wherein the output value iscommunicated between the upstream neuron layer and the downstream neuronlayer without global synchronization of clocks between the upstreamneuron layer and the downstream neuron layer.

In a family of alternative embodiments, the capacitor associated withthe upstream neuron is not in fact ramped down by discharging it, butinstead its voltage is compared to a steadily increasing ramp, and theduration between the initial trigger of this ramp and the time at whichthe ramp voltage passes the capacitor voltage encodes the analog voltagefor transmittal to the remote locale.

In another family of alternative embodiments, the duration arriving atthe downstream neuron is not digitized, but instead immediately appliedto the crossbar array of synaptic devices at that neuron, leading tointegration onto a series of capacitors at the next layer of neuronseven further downstream from this downstream neuron. Embodiments inwhich the incoming duration information is both digitized and is applieddirectly to the downstream synaptic array are also possible.

In yet another embodiment, the present invention provides a systemimplemented in an Artificial Neural Network (ANN), the ANN comprising aplurality of neurons arranged in layers, the system comprising: (a) afirst circuit in a downstream neuron layer, the input of the downstreamneuron layer connected to an output of the upstream neuron layer, thefirst circuit comprising a digital counter and a plurality offlip-flops; (b) a second circuit in an upstream neuron layer, the secondcircuit comprising: (i) a third circuit to generate an enable signal fordischarging a capacitor, the capacitor having an initial valuerepresentative of an output of the upstream neuron layer; (ii) a fourthcircuit to share the generated enable signal to an input of the digitalcounter, where the counter, upon reception of the enable signal, startsan upward count from zero using a clock that is local to the downstreamneuron layer; (iii) a fifth circuit to monitor output analog voltage ofthe capacitor, and (iv) a sixth circuit to transmit a voltage transitionsignal to the plurality of flip-flops in the first circuit in thedownstream neuron layer when a voltage transition is detected in themonitored output analog voltage, wherein the downstream neuron layerlatches current value of the counter upon reception of the voltagetransition signal, the latched current value being equal to the initialvalue representative of an output of the upstream neuron layer, whereinthe output value is communicated between the upstream neuron layer andthe downstream neuron layer without global synchronization of clocksbetween the upstream neuron layer and the downstream neuron layer.

In another embodiment, the present invention provides a methodimplemented in an Artificial Neural Network (ANN), the ANN comprising aplurality of neurons arranged in layers, the layers comprising at leastone upstream neuron layer and at least one downstream neuron layer, theoutput of the at least one upstream neuron layer connected to the inputof the at least one downstream neuron layer, the method comprising: (a)commencing ramping of a threshold voltage for comparison to an outputanalog voltage associated with a capacitor in the upstream neuron layerbased on an enable signal generated in the upstream neuron layer, wherean initial value of the voltage associated with the capacitor representsan output of the upstream neuron layer; (b) sharing the enable signal in(a) to an input of a digital counter located at the downstream neuronlayer, where the counter, upon reception of the enable signal, startingcounting using a clock that is local to the downstream neuron layer; (c)monitoring the ramped threshold voltage in (a) and detecting atransition at which the ramped threshold voltage passes the outputanalog voltage of the capacitor in the upstream neuron layer; and (d)when a voltage transition is detected in the monitored output analogvoltage, (e) transmitting a voltage transition signal to the downstreamneuron layer, wherein the downstream neuron layer latches a currentvalue of the counter upon reception of the voltage transition signal,the latched current value being equal to the initial valuerepresentative of an output of the upstream neuron layer and wherein theoutput value is communicated between the upstream neuron layer and thedownstream neuron layer without global synchronization of clocks betweenthe upstream neuron layer and the downstream neuron layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure, in accordance with one or more various examples,is described in detail regarding the following figures. The drawings areprovided for purposes of illustration only and merely depict examples ofthe disclosure. These drawings are provided to facilitate the reader'sunderstanding of the disclosure and should not be considered limiting ofthe breadth, scope, or applicability of the disclosure. It should benoted that for clarity and ease of illustration these drawings are notnecessarily made to scale.

FIG. 1 illustrates a layer of an ANN implemented on a crossbar array,with pairs of NVM conductances acting as synaptic weights.

FIG. 2 illustrates current mirrors that are used to replicate theinstantaneous currents in the crossbar onto an output stage, such thatthese currents are integrated onto an output capacitance whose finalvoltage represents the analog activation of the neuron Mi.

FIG. 3 illustrates how an enable signal which starts the analogdischarge is shared with a counter associated with the downstream neuronlayer.

FIG. 4 illustrates a sample circuit where a single counter at thedownstream crossbar array can be shared by multiple digitizingflip-flops.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

While this invention is illustrated and described in a preferredembodiment, the invention may be produced in many differentconfigurations. There is depicted in the drawings, and will herein bedescribed in detail, a preferred embodiment of the invention, with theunderstanding that the present disclosure is to be considered as anexemplification of the principles of the invention and the associatedfunctional specifications for its construction and is not intended tolimit the invention to the embodiment illustrated. Those skilled in theart will envision many other possible variations within the scope of thepresent invention.

Note that in this description, references to “one embodiment” or “anembodiment” mean that the feature being referred to is included in atleast one embodiment of the invention. Further, separate references to“one embodiment” in this description do not necessarily refer to thesame embodiment; however, neither are such embodiments mutuallyexclusive, unless so stated and except as will be readily apparent tothose of ordinary skill in the art. Thus, the present invention caninclude any variety of combinations and/or integrations of theembodiments described herein.

A preferred embodiment of the invention described here can eliminatechallenges related to synchronization of clock signals and slew in data,by encoding data into analog delays and digitizing only at thedestination/downstream crossbar array. A preferred embodiment of theinvention introduces an initial trigger signal at the source/upstreamcrossbar array, which traverses the same distance as the subsequent datasignals. Both trigger and data signals are thus subject to the same sleweffects and the same delays, at least to first order. This approach iswell-suited to contexts where the overall application is resilient tosmall, zero-mean errors in the transmitted data, such as an ArtificialNeural Network.

In a preferred embodiment, once the integration operations of chargeonto the capacitors in the upstream neurons has fully completed, anenable signal is generated by the control logic of the upstream crossbararray. This enable signal is used to commence discharge of the analogvoltage stored on the capacitor in each output neuron, or alternatively,to commence a ramped voltage for use in comparing to these analogvoltages. The enable signal is also transmitted to the input of adigital counter that is located at the downstream array. When received,the counter will start an upward count from zero using a clock whichneed only be synchronous in the local region of the downstream,destination array.

FIG. 3 illustrates how the enable signal, which starts the analogdischarge, is shared with the counter in the output stage. When thecomparator rising edge arrives at the FFs, the instantaneous value ofthe counter is captured. This value is a digital representation of theanalog voltage on the upstream output capacitor and is stored locally inthe downstream array, since both the arriving signals are subject to thesame delays.

At some point in time, the capacitor voltage will drop below a referencevoltage close to zero, or the stationary undischarged capacitor voltagewill be passed by the reference voltage ramp. This will cause the outputof a comparator, attached to both the output capacitance node and thereference voltage to undergo a ‘0’ to ‘1’ transition. This rising edgewill be transmitted to the downstream array, where a bank of flip-flopsreceiving inputs in parallel from the outputs of the local counter canlatch in the current values of the counter bits when this rising edge isreceived. While there is a non-negligible propagation delay from theoutput of the comparator (which is local to the upstream array) and thereceiving flip-flops (which are local to the downstream array), thisdelay is comparable to, and is thus effectively offset by, the delay inthe enable signal that commenced the counter operation. Thus, withoutneeding to globally synchronize clocks across the chip, it is possibleto effectively transmit information.

The idea can be extended to a single shared counter at the downstreamarray, with multiple rising edges from different comparators latching inthe instantaneous counter value to different flip-flops at variousinstances in time. As before, so long as the distances are comparable,the latched in value is expected to be a reasonable approximateestimation of the ‘true’ analog voltage.

Potentially, both the trigger/enable signal and the comparator signalcan be conveyed on a multi-wire bus, such that the data pattern on thisbus encodes the address of the capacitor from which the signaloriginated, and thus the address of the particular flip-flop whichshould be latched at the instant of arrival of this data pattern. Thedelays associated with encoding this address at the source array, and ofdecoding this address at the destination, need only be identical foreach and every capacitor/flip-flop pair, and can be added into the delayassociated with the arrival of the trigger signal. If this is donecorrectly, the first delay at the source between triggering capacitivereadout and the transition of the comparator, and the second delay atthe destination between triggering of the counter and the latching ofthe associated flip-flop, will differ by a constant value, which can beengineered to be zero or non-zero as desired. However, this approachcould potentially cause some data values to be conveyed incorrectly dueto contention (too many comparators tripping within the same short timewindow). Some tolerance to contention could be designed in bytransmitting both a physical address and an encoded delay (afterphysical address decoding) to be imposed before latching. Thus, severalsimultaneous comparator events would be transmitted using theappropriate physical addresses and several different encoded delays suchthat the latching events at the destination occurred nearlysimultaneously and at the desired delay (e.g., counter value).

FIG. 4 illustrates a sample circuit where a single counter at thedownstream crossbar array can be shared by multiple digitizingflip-flops. Each arriving rising edge will independently capturedifferent instantaneous values of this counter, depending on the exactarrival time.

In another embodiment, the present invention provides a methodimplemented in an Artificial Neural Network (ANN), the ANN comprising aplurality of neurons arranged in layers, the layers comprising at leastone upstream neuron layer and at least one downstream neuron layer, theoutput of the at least one upstream neuron layer connected to the inputof the at least one downstream neuron layer, the method comprising: (a)commencing discharging of a capacitor in the upstream neuron layer basedon an enable signal generated in the upstream neuron layer, thecapacitor having an initial value representative of an output of theupstream neuron layer; (b) sharing the enable signal in (a) to an inputof a digital counter located at the downstream neuron layer, where thecounter, upon reception of the enable signal, starting an upward countfrom zero using a clock that is local to the downstream neuron layer;(c) monitoring output analog voltage of the capacitor and, when avoltage transition is detected in the monitored output analog voltage,(d) transmitting a voltage transition signal to the downstream neuronlayer, and wherein the downstream neuron layer latches current value ofthe counter upon reception of the voltage transition signal, the latchedcurrent value equal to the initial value representative of an output ofthe upstream neuron layer and where the output value is communicatedbetween the upstream neuron layer and the downstream neuron layerwithout global synchronization of clocks between the upstream neuronlayer and the downstream neuron layer.

In a family of alternative embodiments, the capacitor associated withthe upstream neuron is not in fact ramped down by discharging it, butinstead its voltage is compared to a steadily increasing ramp, and theduration between the initial trigger of this ramp and the time at whichthe ramp voltage passes the capacitor voltage encodes the analog voltagefor transmittal to the remote locale.

In another family of alternative embodiments, the duration arriving atthe downstream neuron is not digitized, but instead immediately appliedto the crossbar array of synaptic devices at that neuron, leading tointegration onto a series of capacitors at the next layer of neuronseven further downstream from this downstream neuron. Embodiments inwhich the incoming duration information is both digitized and is applieddirectly to the downstream synaptic array are also possible.

In yet another embodiment, the present invention provides a systemimplemented in an Artificial Neural Network (ANN), the ANN comprising aplurality of neurons arranged in layers, the system comprising: (a) afirst circuit in a downstream neuron layer, the input of the downstreamneuron layer connected to an output of the upstream neuron layer, thefirst circuit comprising a digital counter and a plurality offlip-flops; (b) a second circuit in an upstream neuron layer, the secondcircuit comprising: (i) a third circuit to generate an enable signal fordischarging a capacitor, the capacitor having an initial valuerepresentative of an output of the upstream neuron layer; (ii) a fourthcircuit to share the generated enable signal to an input of the digitalcounter, where the counter, upon reception of the enable signal, startsan upward count from zero using a clock that is local to the downstreamneuron layer; (iii) a fifth circuit to monitor output analog voltage ofthe capacitor and, when a voltage transition is detected in themonitored output analog voltage, (iv) a sixth circuit to transmit avoltage transition signal to the plurality of flip-flops in the firstcircuit in the downstream neuron layer, wherein the downstream neuronlayer latches current value of the counter upon reception of the voltagetransition signal, the latched current value equal to the initial valuerepresentative of an output of the upstream neuron layer, and whereinthe output value is communicated between the upstream neuron layer andthe downstream neuron layer without global synchronization of clocksbetween the upstream neuron layer and the downstream neuron layer.

In another embodiment, the present invention provides a methodimplemented in an Artificial Neural Network (ANN), the ANN comprising aplurality of neurons arranged in layers, the layers comprising at leastone upstream neuron layer and at least one downstream neuron layer, theoutput of the at least one upstream neuron layer connected to the inputof the at least one downstream neuron layer, the method comprising: (a)commencing ramping of a threshold voltage for comparison to an outputanalog voltage associated with a capacitor in the upstream neuron layerbased on an enable signal generated in the upstream neuron layer, wherean initial value of the voltage associated with the capacitor representsan output of the upstream neuron layer; (b) sharing the enable signal in(a) to an input of a digital counter located at the downstream neuronlayer, where the counter, upon reception of the enable signal, startingcounting using a clock that is local to the downstream neuron layer; (c)monitoring the ramped threshold voltage in (a) and detecting atransition at which the ramped threshold voltage passes the outputanalog voltage of the capacitor in the upstream neuron layer; (d)transmitting a voltage transition signal to the downstream neuron layer,and wherein the downstream neuron layer latches current value of thecounter upon reception of the voltage transition signal, the latchedcurrent value equal to the initial value representative of an output ofthe upstream neuron layer and where the output value is communicatedbetween the upstream neuron layer and the downstream neuron layerwithout global synchronization of clocks between the upstream neuronlayer and the downstream neuron layer.

It is understood that any specific order or hierarchy of steps in theprocesses disclosed is an illustration of example approaches. Based upondesign preferences, it is understood that the specific order orhierarchy of steps in the processes may be rearranged, or that allillustrated steps be performed. Some of the steps may be performedsimultaneously. For example, in certain circumstances, multitasking andparallel processing may be advantageous.

The various embodiments described above are provided by way ofillustration only and should not be construed to limit the scope of thedisclosure. Those skilled in the art will readily recognize variousmodifications and changes that may be made to the principles describedherein without following the example embodiments and applicationsillustrated and described herein, and without departing from the spiritand scope of the disclosure.

CONCLUSION

A system and method has been shown in the above embodiments for theeffective implementation of a system, method and an article ofmanufacture for synchronization-free transmittal of neuron values in ahardware artificial neural network. While various preferred embodimentshave been shown and described, it will be understood that there is nointent to limit the invention by such disclosure, but rather, it isintended to cover all modifications falling within the spirit and scopeof the invention, as defined in the appended claims. For example, thepresent invention should not be limited by software/program, computingenvironment, or specific computing hardware.

1. A method for transmitting signals from one region on-chip to another region on-chip, without using a global clock or other means of global synchronization, the method comprising: transmitting a plurality of analog signals on a plurality of transmission channels, all of the transmission channels sharing a common initialization trigger, by encoding each of the signals in the delay between the common initialization trigger and a subsequent unique termination trigger, so that each of the signals is accurately digitized remotely using a limited number of transmission channels.
 2. The method of claim 1, in which an addressing scheme allows arriving signals on a multi-bit data bus to determine the particular destination circuit node to which the data must be directed.
 3. The method of claim 1, in which an additional level of encoding avoids conflicts caused by nearly simultaneous arrival of two or more signals, where both the arriving address and an associated additional delay determine the particular destination circuit node to which the data must be directed.
 4. The method of claim 1, wherein the plurality of analog signals is used in an analog manner at said another region without conversion of the analog signals to a digitized form. 